Design and Application of All-Digital Delay-Locked Loop and All-Digital Phase-Locked Loop
Date Issued
2010
Date
2010
Author(s)
Wang, You-Jen
Abstract
This thesis describes digital implementations and applications of analog circuits for delay-locked loop (DLL) and phase-locked loop (PLL). Compared with analog DLLs and PLLs, the all-digital DLLs and all-digital PLLs have the benefits such as easy process migration, no passive loop filter needed, and fast locked time. Therefore, digital equivalent implementations of analog circuits are more popular, such as delay-locked loop (DLL), phase-locked loop (PLL), clock and data recovery circuit (CDR), and frequency synthesizer.
There are four works in this thesis: all-digital DLL, PLL, CDR and frequency synthesizer. First, an all-digital DLL with adjustable duty cycles is proposed. The phase and duty cycle of output clock are fast adjusted by the time-to-digital conversion result of the input period. Therefore, the phase alignment and the duty cycle of output clock are assured in 10 cycles of input clock.
Second, a 15KHz-1.39GHz all-digital PLL with frequency multiplication by 1 to 32768 is presented. The frequency counting and binary searching methods are applied to reduce the locked time. And a programmable divider is proposed for wide frequency range applications. Furthermore, the timing resolution of the proposed digitally-controlled oscillator (DCO) is improved to 0.013ps by the capacitance difference among the varactors.
Third, a 6.34Mbps-1.5Gbps all-digital wide-range CDR circuit is presented. The proposed frequency-searching algorithm reduces the frequency locked time and eliminates the harmonic locking problem over wide-range data rates. The CDR circuit has been fabricated in 90nm CMOS process, and parts of this circuit is digital synthesized and reduce the area to 0.00368mm2, smaller than previous publish works.
Finally, an all-digital frequency synthesizer with cancellation, calibration, and correction loops is presented. The proposed cancellation, calibration and correction loops reduce the fractional spur and phase noise of output clock. And the cancellation, calibration and correction loops are digital synthesized to reduce silicon area. Furthermore, the frequency resolution of the proposed DCO is improved by adjusting the difference of control voltage between the two varactors with small capacitance difference. And a high-gain time amplifier is proposed to reduce the offset of D flip-flops.
Subjects
all-digital
Delay-Locked Loop
Phase-Locked Loop
Clock and Data Recovery Circuit
Frequency Synthesizer
Digital-Controlled Oscillator
Type
thesis
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