High Performance Decoder Design for Convolutional LDPC Codes
Date Issued
2007
Date
2007
Author(s)
Chen, Mu-Chung
DOI
en-US
Abstract
This thesis describes the proposed design of Convolutional Low-Density Parity Check Code (LDPC-CC) decoder. Due to increasing high data transmissible rate, data protection techniques are applied to all data transmission and storage devices. Hence, LDPC block codes (LDPC-BC) have been studied over the past years due to their exceptional decoding performance on a wide variety of communication channels. Their block-counterparts, LDPC-CC codes were first proposed in 1999 and proved that those codes have similar bit-error rate (BER) performance. However, LDPC-CC codes have several advantages over LDPC-BC codes. First of all, LDPC-CC requires less latency than LDPC-BC codes for long block-length codes. Thus, it is very suitable to integrating LDPC-CC codes to iterative decoding, such as combining inner codes with outer codes in multiple-input multiple-output (MIMO) communication system, rather than integrating with LDPC-BC. In hardware architectural point of view, encoders and decoders of LDPC-CC are easier to be implemented. Based on the previous works on LDPC-CC codes, further optimization can be achieved. In order to save clock cycles, construction of a parity-check matrix is altered. For saving even more clock cycles, by changing the order of calculation sequences, dual-port SRAM is applied to our design. Some of circuit techniques, such as Wallace tree structure and linear approximation, are applied in our design in order to improve the throughput of the proposed decoder. The details of the optimizations are discussed in this thesis. In conclusion to our design, approximately 50% of clock cycles are saved comparing to [7] and 50% of the power consumption is saved compared to [8].
Subjects
迴旋式低密度奇偶檢查碼
錯誤更正碼
Convolutional LDPC Codes
LDPC-CC
Error Correcting Codes
Type
thesis
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