DESIGN OF HYBRID- CLUSTERING ALGORITHM FOR LOW POWER SCAN CHAINS
Date Issued
2005
Date
2005
Author(s)
Hsieh, Ping-Hsun
DOI
en-US
Abstract
The use of scan-based architectures is wide-spreading in circuit testing processes nowadays, yet expensive in power consumption. Scan chain reordering techniques have been utilized for years to reduce power dissipation in traditional DfT (Design for Test); nevertheless, one of the main concerns, namely the length of scan routing, has received a plenty of attention for the reason of a tradeoff existing between power reduction and length reduction of wire connections. Hence, in this thesis, a hybrid clustering algorithm named ISAC (Intrinsic Structure Approximation-based Clustering) consisting of OPTICS and k-means is proposed. ISAC adopts information, obtained by OPTICS, from the intrinsic structure of the distribution associated with scan cells to determine the number of clusters generated by k-means in which k compact circle-like clusters are formed. A property of geometry has been proved that given a diameter, a circle-like cluster can cover the maximum area; thereby it might be able to contain as many cells as possible. Results from our quantitative simulations in the benchmark circuit s9234 have demonstrated the efficiency of ISAC in both power reduction and length saving; both reduced up to 16.563% and 65.989%, respectively.
Subjects
電路測試
低功率
掃描鏈
circuit testing
low power
scan chain
Type
thesis