Low-Voltage Low-Power CMOS Multiplier Design Using Pipeline Latch High-Level Synthesis Approach
Date Issued
2010
Date
2010
Author(s)
Wu, Wei-Hong
Abstract
The integrate-circuit technology scale down recently, more functionality can be combined into a single chip. So circuit complexity thereupon increases, performance and power consumption will be considered.
The thesis describe a ways to increase speed of a circuit, and make up the high-level circuit. Chapter 1 introduce CMOS very large scale integrated circuits reason, power consumption and simulation software .
Chapter 2 introduces a 16-bit Wallace tree multiplier circuit with VDD = 0.5V. Latch technology insert the multiplier become pipeline structure. Using Synopsys Primetime EDA tool analyses result, We can get the 257% increase operation frequency. Because of the final adder is bigger delay than other path of the multiplier circuit, so we can get the 95% increase operation frequency by change the VDD = 1V.
Chapter 3 introduces a high-level multiplier circuit consists of 16-bit multiplier circuits, compare with high-level Wallace multiplier, performance and power consumption have not been improved, but is easily scalable to higher bit precision by duplicating sub-multiplier and adding an additional levels of reduction, allows for short design time. We have a way to increase speed by insert pipeline latch into final adder of the high-level multiplier.
Subjects
Pipeline
Latch
Multiplier
Type
thesis
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