A Low-Jitter Clock and Data Recovery Circuit with Wide-Linear-Range Frequency Detector
Date Issued
2007
Date
2007
Author(s)
Lee, Ming-Hwa
DOI
en-US
Abstract
In recent years, the speed of serial communication has been increased to multi-gigabits per second. The large demand of bandwidth converts the transmission medium from copper wire to fiber gradually. For both local area networks (LANs) and wide area networks (WANs), 10GBASE Ethernet plays an important role because of the low cost. In the receiver side, clock and data recovery (CDR) circuits can be employed to generate the clocks synchronized with received data and remove the jitter of input random data. Traditionally, GaAs MESFET or Si bipolar technology is usually used for implementing such high speed circuits. However, CMOS technologies are now considered in these high-speed circuits because of the low cost, low power dissipation, and highly integrated capability.
Designed for the applications of 10GBASE-LX4 Ethernet, a 3.125-Gb/s CDR is proposed to lower the output clock jitter and decrease the frequency acquisition time by employing a low-jitter Hodge phase detector and a wide-linear-range frequency detector. Due to the requirement of the small loop bandwidth of CDR, pull-in range is limited and CDR without frequency acquisition loops might need additional reference clocks. Digital quadricorrelator techniques are widely used for frequency acquisition loops because of the tolerance to process, voltage, and temperature variations. In this work, a modified frequency detector is proposed to widen linear range, which can decrease the frequency acquisition time. Besides, a low-jitter Hogge phase detector is also proposed to minimize output clock jitter with no need of loop bandwidth change. This chip is fabricated in a 0.18-μm 1P6M CMOS technology and occupies a chip area of 0.61 mm × 0.61 mm. The output jitter of this proposed CDR is measured 70 ps (peak-to-peak) and 8.3 ps (rms), and the measured bit-error rate (BER) is less than 10-12 for 231-1 PRBS. The power dissipation of core circuit is 61 mW from a single 1.8-V power supply.
Subjects
資料時脈回復電路
相位偵測器
Clock and Data Recovery
Phase Detector
Type
thesis