Design of Low-Power, Low-Voltage Continuous-Time Delta-Sigma Modulator
Date Issued
2005
Date
2005
Author(s)
Wu, Chun-Kuan
DOI
zh-TW
Abstract
Recently, the wireless communication systems become an important tool for data link, and the specification varies day by day. Developing the high-performance circuits for wireless communication systems is an important issue.
The thesis focuses on the analog-to-digital converter in receiver design. The continuous-time delta-sigma ADC is suitable for high-performance receiver design because of the high resolution in low-voltage, and low-power operation. Therefore, we emphasize on the research of continuous-time delta-sigma ADC.
In this work, a dual-mode continuous-time delta-sigma ADC is designed and implemented for the diversity of current communication architectures. In order to achieve low-voltage, and low-power design, two new design methods are proposed: 1. Active gain enhancement OTA, 2. Sliding quantizer, and will be discussed next.
The chip is designed with a 1.2-V power supply using 0.18-μm TSMC CMOS process and the power consumption is 1.2 mW. The post-layout simulation result shows that the ADC achieves a 68-dB signal-to-noise ratio (SNR) within a 1-MHz bandwidth centered at 2-MHz in band-pass mode; and 63-dB SNR in 1.92-MHz bandwidth within the low-pass mode. Both with a sampling rate of 48 MHz.
Subjects
連續型
三角積分
continuou-time
delta-sigma
Type
thesis
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