Circuit Design for the LDPC Codec Using Interblock Memory
Date Issued
2006
Date
2006
Author(s)
Chou, Hong-Fu
DOI
en-US
Abstract
It has been shown that by properly introducing interblock memory to binary LDPC code, the decoded error rates can be significantly reduced for short code length.
However, the price is the increased decoding delay and decoding complexity. In this thesis, we conduct both the circuit design of LDPC codec and LDPC with interblock
memory codec. Then, we compare the performance of both coding scheme based on complexity and the error rate.
For the LDPC encoder, we consider two kinds of approaches. One was proposed by Richarson and was implemented by Parhi and the other is the generation matrix implemented by look up table. The decoder approach is implemented with partial
parallel architecture.
For the decoder of the LDPC code with interblock memory, it has been shown that there are two possible designs. One is the feedforward-only decoding and the other is the decoding with the feedback feature. In this thesis, we also compare the advantage and disadvantage of both designs based on the view of circuit application.
Subjects
區塊記憶
低密度同位元檢查碼
電路設計
Interblock memory
LDPC
circuit design
Implementation
Type
thesis