Cell Stability and Write Improvement of 2T (Footprint) Stacked SRAM
Journal
2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022
Date Issued
2022
Author(s)
Abstract
Stacking 4 n-type vertical gate-all-around transistors (VFETs) on 2 pFinFETs can scale down a 6T SRAM bitcell into the footprint of only 2 transistors. The minimum operation voltage (Vmin) considering workfucntion (WF) variation can be reduced to 0.59V by tuning pFET fin height (Hfin) to 15nm and nFET gate length (Lgn) to 20nm without increasing bitcell area. Applying the negative bitline (NBL) level of -80mV can further increase the write speed by 10%. © 2022 IEEE.
Other Subjects
6T-SRAM; 6T-SRAMs; Bitcell; Cell stability; Fin height; Gate-all-around transistors; Gate-length; Operation voltage; Scale-down; Stackings
Type
conference paper