A 1.1 G MAC/s sub-word-parallel digital signal processor for wireless communication applications
Journal
IEEE Journal of Solid-State Circuits
Journal Volume
39
Journal Issue
1
Pages
169-183
Date Issued
2004-01
Author(s)
Abstract
https://www.scopus.com/inward/record.uri?eid=2-s2.0-0742268978&doi=10.1109%2fJSSC.2003.820861&partnerID=40&md5=dc230c9f57e2afe58abf267deff05ef0
This work proposes a communication digital signal processor (DSP) suitable for massive signal processing operations in orthogonal frequency division multiplexing (OFDM) and code-division multiple-access (CDMA) communication systems. The OFDM-based IEEE 802.11a wireless LAN transceiver and CDMA-based WCDMA uplink receiver are simulated to evaluate the computation requirements of future communication systems. The architecture of the communication digital signal processor is established according to the computational complexity of these simulations. The proposed architecture supports basic butterfly operations, single/double-precision and real- and complex-valued multiplication-and-accumulation (MAC), squared error computation, and add-compare-select (ACS) operation. This butterfly/complex MAC architecture can greatly enhance the execution efficiency of operations often found in communication applications. The processor chip is fabricated using a 0.35-μm n-well one-poly four-metal CMOS technology. The fabricated DSP chip reaches a speed of 1.1 G MAC/s when operating in the high-speed mode, and it achieves 4 M MAC/s/mW in the low-power mode.
Subjects
Digital signal processor (DSP); Sub-word parallelism; Wireless communication
Other Subjects
CMOS integrated circuits; Code division multiple access; Computational complexity; Integrated circuit manufacture; Local area networks; Microprocessor chips; Orthogonal frequency division multiplexing; Telecommunication links; Transceivers; Wireless telecommunication systems; Multiplication and accumulation; Sub-word parallelism; Wideband code division multiple access; Digital signal processing
Type
journal article