CMOS Millimeter-Wave Circuits and Architecture Design Techniques for High Date Rate Receiver

Recently, the interest in millimeter-wave radio links has increased. This is caused by application that needs wireless radio links with high data rates. By using today''s advanced CMOS technologies, it allows relatively cheap implementations for such radio links. The short wavelength of the millimeter-wave signals suffer from the serious attenuation in the atmosphere and multi-path channels, which hinders the wireless communication from achieving high SNR performance required by high throughput system specifications. This puts special requirements on system design, architecture and circuits.
This dissertation investigated circuit design techniques operating at the millimeter-wave frequency using advanced 65nm, 90nm and 130nm CMOS technologies. The goal of the research is to realize high-speed, low-power, and compact integrated wireless communication key blocks operating at 60 GHz frequency. The various current-reused and noise cancelling LNA circuits and receiver building blocks toward the realization of the low power and low noise millimeter-wave systems are presented in this dissertation. On the system side, a fully integrated dual-antenna phased-array RF front-end receiver including the active phase shifter has been demonstrated. A less complex analog FSK demodulator using an injection-locked technique to achieve a gigabit data rate without suffering from process variation is also exhibited.
The proposed dual-antenna phased-array RF front-end receiver was designed and fabricated in a 0.13um RF CMOS process. In order to obtain good common-mode noise rejection, the receiver front-end employs fully differential architecture. The proposed gm-boosted current-reuse LNA circuit mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate down conversion mixer alleviates the problem of the third harmonic of the LO as well. An active all-pass filter is employed to adjust the phase shift of each LO signal. This architecture exhibits a measured SNR improvement of 4.5 dB with an overall measured gain of 34.5 dB. Overall chip power consumption is 93mW.
The proposed injection-locked high data-rate FSK/MSK demodulator is fabricated in a 0.13um CMOS RF technology. Compared with the conventional LC tank discriminator, the injection-locked oscillator provides a process insensitive frequency-to-phase transformation for analog non-coherent FSK/MSK demodulation. The measured demodulation input sensitivity is -12dBm at BER less than 10^-9 for uncoded 2.5Gbps 2^31-1 PRBS data with 0.5 modulation index. The whole chip consumes 20mW from a 1.2V supply voltage, where the FSK/MSK demodulator core circuit only consumes 6mW.