Design and Implementation of High-speed and Low-jitter Delay-locked Loops

With the evolution and scaling down of CMOS technologies, the demand for high-speed and high integration density VLSI system has recently grown exponentially. Hence, this thesis illustrates the implementation of the high speed delay-locked loops (DLLs). However, the operating frequency of typical DLL is drastically limited by phase detector and charge pump because of their slow movement. Besides, the current mismatch of charge pump will result in a significant static phase error. Moreover, the output’s jitter peaking due to input clock noise also degrades the system performance. In this thesis, design considerations and realization about the proposed architectures are presented in order to increase the system speed and improve the jitter performance.
Firstly, a high-speed delay-locked loop architecture implemented with 0.18-μm CMOS process is presented. Using the frequency divider in front of the phase detector, the operating frequency of phase detector and charge pump can be alleviated. Furthermore, using the quadratic-phase generated by the divider, the ripple on controlled-line can be lowered and the jitter performance can improve. The analysis of jitter transfer function (JTF) and building block circuit design are illustrated. Therefore, a high-speed DLL is realized and the measurement results are also described.
In the second work, a DLL incorporating multi-band delay line technique is proposed. With a reduced KVCDL architecture, the noise amount coupling from the controlled-line ripple can be suppressed evidently and obtain better jitter behavior. Moreover, the divider circuit, which places before the phase detector, can enlarge the equivalent detectable range of the PD and the harmonic locking problem can be avoided. Implemented with standard TSMC 0.18-μm CMOS process, a 2.8-GHz low-jitter DLL is proposed and the measurement results are also demonstrated.