Signal and Power Integrity Co-Simulation and Analysis for DDR3 Memory on Industrial Platform PCBs
Date Issued
2014
Date
2014
Author(s)
Chen, Yong-Lin
Abstract
With the clock and data rate increasing nowadays, the signal/power integrity co-simulation is necessary. The major theme of this thesis is to investigate how the electromagnetic effect and coupling mechanism affect the signal/power integrity of a whole system in recent high-speed-digital system. The achievement is to optimize the electrical performance of a system by co-simulating and analyzing.
There are two major parts in this thesis. First, the signal/power integrity will be researched as the signal is under pull up and pull down situations in two-layer coupled transmission line. The coupling mechanism of noise from power transmission line to signal transmission line and the fluctuation of power transmission line are analyzed, which lead to the abnormal waveform on signal.
Then, the integrity/power integrity co-simulation is analyzed on DDR memory bus on industrial PCB. There are two types of data line routing on industrial PCB: (i) microstrio to microstrip (ii) microstrip to strip-line. The time domain responses and eye-diagrams of these two types are investigated in this thesis. Besides, the simplified I/O buffer model with circuit consideration is also proposed in the thesis. Main contribution of proposed I/O buffer is to fully consider the capacitance effect of I/O circuit. Applying the proposed I/O buffer on DDR3 eight data lines (one byte) can obtain improved eye height and rising/falling time compared with conventional I/O buffer while eight data lines switch simultaneously. The simulation results using the proposed I/O buffer correlate with measurement results measured by oscilloscope. The error percentage is smaller than 5%, and shows the proposed I/O buffer is reliable and accurate.
Subjects
訊號/電源完整度共模擬與分析
輸入/輸出緩衝器模器
耦合傳輸線
工業主機板
第三代雙倍資料率記憶體
Type
thesis
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