An IP Generator for Quasi-Cyclic LDPC Convolutional Code Decoders
Journal
IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
Pages
1652-1655
Date Issued
2008-11
Author(s)
Abstract
In this paper, the design and implementation of a high performance soft LDPC-CC decoder IP generator is presented. The proposed design is based on quasi-cyclic (QC) low-density parity-check matrices. These matrices not only simplify decoder design but also require less memory storage. A special digital processor is proposed to reduce the critical path and enhance the throughput. In addition, we have designed an IP generator and associated user interface that can take specifications of three parameters: iteration number, memory length, and code rate. With this generator, high-performance LDPC-CC decoders conforming to the user's specifications can be generated effortlessly. © 2008 IEEE.
SDGs
Other Subjects
Code rates; Critical paths; Decoder designs; Digital processors; Iteration numbers; LDPC convolutional codes; Low density parity checks; Memory lengths; Memory storages; Quasi-cyclic; Three parameters; Communication channels (information theory); Convolutional codes; Internet protocols; Security of data; Specifications; User interfaces; Decoding
Type
conference paper