A 15-Gb/s 2:1 multiplexer in 0.18-μm CMOS
Journal
IEEE Microwave and Wireless Components Letters
Journal Volume
16
Journal Issue
10
Pages
558-560
Date Issued
2006
Author(s)
Abstract
By employing the inductive peaking technique and the super-dynamic flip-flops, a 2:1 multiplexer (MUX) is presented for high-speed operations. The proposed circuit is realized in a 0.18-μm CMOS process. With a power consumption of 110mW from a 2-V supply voltage, the fully integrated MUX can operate at an output rate up to 15Gb/s. From the measured eye-diagrams, the 15-Gb/s half-rate MUX exhibits an output voltage swing of 225mV and a root-mean-square jitter of 2.7ps.
SDGs
Type
journal article