The Acceleration of Pipeline Workloads under the FPGA Area and Bandwidth Constraints
Date Issued
2014
Date
2014
Author(s)
Huang, Wei-Ning
Abstract
This work is motivated by the advance of heterogeneous computing and the strong demands of workload acceleration in practice. By considering pipeline workloads over FPGA, this thesis explores a systematic methodology to configure the hardware instances of each pipeline stage such that the maximum of the execution time of each stage is minimized, where FPGA allocation with the memory bandwidth constraint is considered. For the target problem, an algorithm is proposed and proved being optimal, and a real implementation study is conducted. In the experimental study, an image filter FPGA implementation can outperform the CPU, GPU, and baseline FPGA solutions by 460%, 73%, and 1030%, respectively. Extensive simulations were also conducted with a large FPGA size to show the scalability of this work.
Subjects
異質運算系統
FPGA
管線工作
加速器
Type
thesis
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