Multilevel Gridless Full-Chip Routing Considering Performance and Manufacturability
Date Issued
2007
Date
2007
Author(s)
Chen, Tai-Chen
DOI
en-US
Abstract
As technology advances into the nanometer era, chips may consist of billions of transistors, and process geometries shrink to 90 nm and below. Further, the minimum feature size becomes significantly smaller than the lithographic wavelength, and thus design shapes on a wafer may have large distortions. For such large and complex designs, it is desirable to develop a new routing system that can cope with the four major modern design challenges: complexity, routability, performance, and manufacturability. In this dissertation, we propose a multilevel gridless full-chip routing system to handle these four design challenges. The system consists of three major parts: (1) the gridless routing model, (2) Optical Proximity Correction (OPC) modeling, and (3) the multilevel framework.
To handle modern routing with nanometer electrical effects, we need to consider designs with variable wire/via widths and spacings, for which gridless routing approaches are desirable due to its great flexibility. We introduce a gridless routing model that can obtain design-rule-correct paths and avoid redundant wires. Besides, we propose an enhanced model for the gridless routing model to reduce the solution space and the runtime. Experimental results show that the proposed gridless models lead to the best routing solution ever reported in the literature.
Due to the sub-wavelength lithography, manufacturing the sub-90 nm feature size requires intensive use of Resolution-Enhancement Techniques (RET's), among which OPC is the most popular technique in industry. Considering OPC during routing can significantly alleviate the cost of post-layout OPC operations. We present rule- and model-based OPC modeling to predict the behavior of a post-layout OPC tool and incorporate the models into our gridless router to reduce the OPC cost. Experimental results show that the great effectiveness of our OPC modeling in reducing the number of pattern features and edge-placement errors.
To cope with the increasing complexity, electronic design automation tools of very large-scale designs are needed. We present a new ``V-shaped' multilevel framework (called VMF) for performance consideration. Unlike the traditional multilevel framework, VMF works in the V-shaped manner: top-down uncoarsening followed by bottom-up coarsening. The VMF outperforms the traditional one in optimizing global circuit effects, since the VMF first considers the global configuration and then processes down to local ones level by level and thus the global effects can be handled at earlier stages. Experimental results show that the VMF achieves the best published routing quality with less wirelength, smaller critical net delay, and smaller average net delay.
Subjects
實體設計
繞線
無格線式繞線
多階層架構
可製造性設計
光學鄰近校正
physical design
routing
gridless routing
multilevel framework
design for manufacturing (DFM)
optical proximity correction (OPC)
Type
thesis
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