VLSI implementation of the motion estimator with two-dimensional data-reuse
Journal
IEEE Transactions on Consumer Electronics
Journal Volume
44
Journal Issue
3
Pages
623-629
Date Issued
1998
Author(s)
Abstract
This paper describes the VLSI implementation with two-dimensional (2-D) data-reuse architecture for full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed VLSI architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates. © 1998 IEEE.
Other Subjects
Algorithms; Computer architecture; Shift registers; Block matching algorithm (BMA); Motion estimators; Processing element (PE) arrays; Two-dimensional data reuse; VLSI circuits
Type
journal article