SoC Platform Design Optimizations for Multimedia Applications-An Example for JPEG2000 Decoders
Date Issued
2007
Date
2007
Author(s)
Chen, Guan-Hong
DOI
zh-TW
Abstract
Platform Architect, one of the CoWare corporation’s electronic system level design tool, can be used to build and simulate various virtual System-on-chip(SoC) platforms. This thesis explores a jpeg2000 decoder on SoC platforms that are based on Transaction-Level Modeling (TLM). We improve the system execution time by using both methods of hardware and software optimizations. In the hardware part, we refine the communication architecture and make use of master ports on the SoC platform to reduce communication time. In the software part, we enable caches, compiler options and rewriting parts of the source code for the different architectures to improve the system execution time. Finally we can get the best solution from exploring the hardware and software optimizations.
Subjects
電子層級設計軟體
處理程序層級
執行時間
系統單晶片
快取記憶體
electronic system level design tool
Transaction-Level Modeling
execution time
System-on-chip
cache
Type
thesis
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ntu-96-J93921035-1.pdf
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