Design and Implementation of Bang-Bang Phase/Frequency Detectors
Date Issued
2007
Date
2007
Author(s)
Lin, Shao-Hung
DOI
en-US
Abstract
This thesis describes the implementation of the bang-bang phase/frequency detectors (PD&FD) used in continuous rate clock and data recovery (CDR) circuit and phase-locked loop (PLL) circuit. In order to achieve continuous rate receivable, FDs with wide frequency locking range are developed. The CDR system or PLL with high reference frequency incorporate the bang-bang phase detector, which is suitable for high speed operation. This thesis is divided into six chapters. Chapter 1 is the introduction. In chapter 2, the various architectures of PD and FD are described.
In chapter 3, the mathematical analysis of the bang-bang loop is presented. The non-linearly characteristic of the bang-bang loop makes the stability requirement differ a lot from the linear loop. Design parameters are also derived from the nonlinear model and equations. The jitter transfer and jitter tolerance function of the bang-bang loop is also introduced.
In chapter 4, three full-rate BBPFDs and a half-rate BBPFD are presented for the continuous-rate CDR circuit. Based on the characteristic of tristate BBPDs, only adding an AND gate can realize the FD function which has unilateral wide frequency locking range. They consume less power than conventional methods and their architectures provide several advantages: small area, less loading on clock buffer, tri-state output, recovering data by itself, wide frequency locking range, etc. In addition, the analytical analysis for the frequency acquisition time has been derived. The experimental results are also given to verify the theoretical analysis. Three continuous-rate CDR circuits are implemented to demonstrate BBPFD’s function. They are fabricated in a standard 0.18 um CMOS process. Measurements show the receivable data rate from 622Mbps to 3.125Gbps and the all bit error rates are below 10-12. Each full-rate continuous-rate CDR circuit consumes about 60mW at 3.125Gbps and core area is 0.1326mm2. The half-rate continuous-rate CDR consumes about 80mW at 3.125Gbps and core area is about 0.09 mm2.
In chapter 5, three full-rate BBPFDs are presented for the BBPLL circuit. Based on the BBPFDs proposed for CDR circuit, an extra NOR gate can realize a FD with bi-direction wide frequency locking range. The proposed BBPFDs eliminate the reset path, hence the operation speed is higher than conventional one. Their frequency locking process has already been analyzed theoretically, and the results match with simulation results. A 2GHz BBPLL is fabricated in a standard 0.18 um CMOS process to verify BBPFD’s function. The power consumption is 30mW, and the chip area is 0.85 x 0.4 mm2. Finally, chapter 6 is the conclusion.
Subjects
鎖相迴路
時脈及資料回復
相位偵測器
頻率偵測器
連續速率
PLL
CDR
PD
FD
continuous-rate
Type
thesis
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