A DFT Technique for Output Offset Voltage Testing of TFT-LCD Source Driver IC

This thesis presents a DFT technique to measure the output offset voltages of TFT-LCD source driver IC. The proposed DFT performs on-chip voltage comparison in parallel so the required number of tester channels is greatly reduced. According to simulation results, the accuracy of output offset voltage measurement is 0.371mV. The proposed technique saves hundreds of I/O pins and reduces the total test time by 51%. The DFT circuitry is implemented on the scribe line so it is non-intrusive to the original design. This DFT layout results in zero area overhead.