Byte-reconfigurable LDPC codec design with application to high-performance ECC of NAND flash memory systems
Journal
IEEE Transactions on Circuits and Systems I: Regular Papers
Journal Volume
62
Journal Issue
7
Pages
1794-1804
Date Issued
2015
Author(s)
Abstract
The reliability of NAND Flash memory deteriorates due to multi-level cell technique and advanced manufacturing technology. To deal with more errors, LDPC codes show superior performance to conventional BCH codes as ECC of NAND Flash memory systems. However, LDPC codec for NAND Flash memory systems faces problems of high redesign effort, high on-chip memory cost and high-throughput demand. This paper presents a byte-reconfigurable cost-effective high-throughput QC-LDPC codec design for NAND Flash memory systems. Reconfigurable codec design is proposed to support various QC-LDPC codes for different Flash memories. To save on-chip memory cost, shared-memory architecture and rescheduling architecture are presented for encoder and decoder, respectively. The shared-memory architecture can save 23% area cost of the encoder and the rescheduling architecture reduces 15% area cost of decoder. In addition, the proposed sub-iteration based early termination (SIB-ET) scheme reduces 29.6% decoding iteration counts compare with the state-of-the-art early termination scheme when raw BER of Flash memory is . Finally, the QC-LDPC codec for NAND Flash memory systems is implemented in TSMC 90 nm technology. The post-layout result shows that the core size is only 6.72 at 222 MHz operating frequency.
SDGs
Type
journal article