Unified Physics-Based CFET Thermal SPICE Considering BEOL, Substrate, and BSPDN Using Adiabatic Cones
Journal
2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
Start Page
1-3
Date Issued
2025-06-08
Author(s)
Chou, Tao
Shen, He-Wen
Lai, Yu-Sheng
Tseng, Chia-Wei
Chang, Fang-Yu
Lin, Hsin-Cheng
Yao, Ching-Wang
Abstract
For the first time, we present the physics-based thermal SPICE of the split-gate complementary FET (CFET). The passage of heat forms the cone/column-shaped adiabatic surfaces from the transistor level to BEOL and the backside, where can be power delivery network (BSPDN) or substrate. The temperature ( relative to the heat sink) of CFET is 2.2 times higher than the non-stacked nanosheet (NS). n-on-p CFET can alleviate temperature by 2°C compared to p-on-n CFET due to the higher thermal resistance of SiGe:B S/D than Si:P S/D. The same physical model is used for each level (devices, BEOL, substrate, and BSPDN) and is represented by Cauer ladders.
Publisher
IEEE
Type
conference paper