CMOS數位/類比式延遲鎖相迴路之設計與應用
Design and Application of CMOS Digital/Analog Delay-Locked Loops
Date Issued
2004
Date
2004
Author(s)
Chang, Hsiang-Hui
DOI
en-US
Abstract
Modern CMOS techniques can not only integrate many digital circuits into a system, but also raise the operating clock frequency of the digital systems. However, the higher operating clock will decrease the timing margin for high-performance digital systems. As the timing margin is tight, the timing skews and jitters would make it difficult to synchronize among IC modules.
Delay-locked loops （DLLs）have been widely used to minimize timing skews and jitters of the clock signals. The DLLs benefit from the unconditional stability, fast locking time and better jitter performance compared with the PLLs. If no frequency synthesis is needed, the DLLs are preferred for the purpose of synchronization. However, various intrinsic problems exist in a conventional DLL such as narrow operation frequency range, harmonic locking, lack of frequency synthesis function, mismatch among delay stages, and unsuppressed VCDL noise. To develop the solutions for the limitations existing in the conventional DLL and realize is the object of this dissertation.
Firstly, a wide-range and fast-locking all-digital DLL is presented to resolve the narrow operating range problem. The cycle-controlled delay unit could enlarge the operating frequency range of the proposed DLL by a factor of 256 without decreasing timing resolution. The trade-off between the number of delay stages and the operating frequency range can be removed in the proposed all-digital DLL.
Secondly, a digital calibration circuit is presented to provide another way to average the mismatch-induced timings in the digital domain when the DLL operates at 2GHz. With the proposed digital calibration circuit, the mismatch-induced timing error among multiphase clocks can be reduced to be less than 1.2X quantization error theoretically.
A DLL-based CDR is presented to resolve the jitter accumulated problems and so achieves both low jitter and multi data rate operation. The MASDLL provides the function of the integer multiplication frequency synthesis to extend the operating frequency range. The shifted-averaging technique is also proposed to average the mismatch-induced timing error among delay stages in the analog domain. A duty-cycle-insensitive phase detector can mitigate the dependency on clock duty cycle variations.
Three DLLs proposed in this dissertation allow more flexibility or more reliable performance for utilizing DLLs in various applications.
Subjects
操作頻率
鎖相迴路
壓控延遲線
延遲鎖相迴路
VCDL
PLL
Operating frequency
DLL
Type
thesis