Design of a high-speed bloc k interleaving/deinterleaving architecture for wireless communication applications
Journal
IEEE International Conference on Consumer Electronics
Date Issued
2009
Author(s)
Abstract
This paper presents a high-speed block interleaver/deinterleaver designed to prevent burst errors in wireless communications. Using FIFO banks, our proposed architecture is a high-speed design that owns lower hardware complexity and consumes lower power dissipation. Especially, the simple finite-state-machine control unit used in our design can provide an arbitrary column-wise permutation for the block interleaver.
Type
conference paper