Design and Implementation of a Fast Convergence LDPC Decoder for IEEE802.16e Standard

In this thesis, we propose the fast convergence scheduling method based on the novel technique named Informed Dynamic Scheduling for low-density parity-check code decoder. In addition, we design the hardware architecture to fit with the proposed method applied to IEEE 802.16e standard which is known as WiMAX. From the computer simulation result, the proposed method decreases the decoding iteration up to 46.92% compared with the horizontal layer decoding algorithm when Signal-to-noise ratio is 1dB and the maximum decoding iteration is 20. Furthermore, the BER performance of our method has only small degradation which can be ignored. We also implement the proposed algorithm on Xilinx FPGA board to verify the correctness. The implementation result shows that the extra hardware cost and memory usage is small. The total system throughput also improves because of the lower decoding iterations. Compare with the origin Informed Dynamic Scheduling method, the complexity of our proposed algorithm is much lower that can be implemented on the hardware easily.