A 1V 5-bit 5GSample/sec CMOS ADC for UWB receivers
Journal
International Symposium on VLSI Design, Automation & Test
Pages
140-143
Date Issued
2007-04
Author(s)
I-Hsin Wang
Abstract
This paper presents a high-speed flash analog-to-digital converter (ADC) for ultra wide band (UWB) receivers. In this flash ADC, the interpolating technique is adopted to reduce the number of the amplifiers and a linear and wide-bandwidth interpolating amplifier is presented. For this ADC, the transistors sizes for the cascaded stages are inversely scaled to improve the trade-off in bandwidth and power consumption. The active inductor peaking technique is also employed in the pre-amplifiers of comparators and the track-and-hold circuit to enhance the bandwidth. Furthermore, a digital-to-analog converter (DAC) is embedded for measurements. This chip has been fabricated in 0.13-mum 1P8M CMOS process and the total power consumption is 113 mW with IV supply voltage. The ADC achieves 4-bit effective number of bits (ENOB) for input signal of 200 MHz at 5-GSample/sec.
SDGs
Type
conference paper