A high-speed conditional carry select (CCS) adder circuit with a successively incremented carry number block (SICNB) structure for low-voltage VLSI implementation
Journal
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Journal Volume
47
Journal Issue
10
Pages
1074-1079
Date Issued
2000
Author(s)
Huang Y.-M
Abstract
This paper reports a conditional carry select (CCS) adder circuit with a successively-increniented-carry-nurnber block (SICNB) structure for low-voltage VLSI implementation. Owing to the successively-incremented-carry-number block (SICNB) structure, the new 16-bit SICNB CCS adder provides a 37% faster speed as compared to the conventional conditional carry select adder based on the SPICE results. © 2000 IEEE.
Subjects
Carry select adders; High-speed; Low-voltage; Multipliers
SDGs
Other Subjects
Conditional carry select adder circuit; Successively incremented carry number block structure; Computer simulation; Electric power supplies to apparatus; Electric waveforms; Gates (transistor); Logic circuits; Logic design; MOS devices; VLSI circuits; Adders
Type
journal article