A 6-b 1-GS/s 30-mW ADC in 90-nm CMOS technology
Journal
Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Pages
45-48
Date Issued
2008
Author(s)
Lien, Y.-C.
Abstract
A 6-b 1-GS/s subranging ADC with THA is implemented in 90-nm CMOS technology. This circuit incorporates folded input for the fine ADC as well as offset calibration and digital correction techniques, achieving greater than 5.2 ENOB and 40-dB SFDR up to the Nyquist, and 1.1-GHz ERBW with power consumption of only 30 mW.
SDGs
Type
conference paper