Floorplan and Power/Ground Network Co-Synthesis for Fast Design Convergence

As technology advances, the metal width decreases while the global wire length in-
creases. This trend makes the resistance of the power wire increase substantially.
Further, the threshold voltage scales nonlinearly, raising the ratio of the threshold
voltage to the supply voltage and making the voltage (IR) drop in the power/ground
(P/G) network a serious problem in modern IC design. Traditional P/G network
analysis methods are often very computationally expensive, and it is thus not feasi-
ble to co-synthesize P/G network with floorplan. To make the co-synthesis feasible,
we need not only an efficient, effective, and flexible floorplanning algorithm, but
also a very efficient, yet sufficiently accurate P/G network analysis method. In this
thesis, we present a method for floorplan and P/G network co-synthesis based on
an efficient P/G network analysis scheme and the B*-tree floorplan representation.
We integrate the co-synthesis into a commercial design flow to develop an effective
power integrity (IR-drop) driven design methodology. Experimental results based on
a real-world circuit design and the MCNC benchmarks show that our design method-
ology successfully fixes the IR-drop errors earlier at the floorplanning stage and thus
enables the single-pass design convergence.