A new VLSI architecture without global broadcast for 2-D digital filters
Resource
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Journal
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Pages
-
Date Issued
2000-05
Date
2000-05
Author(s)
Van, Lan-Da
Tang, Chih-Chun
Shing,Tenqchen
Feng, Wu-Shiung
DOI
N/A
Abstract
In this paper, we propose the new two-dimensional (2-D) systolic-array structures of IIR/FIR digital filters without global broadcast by the different derivation and another systolic transformation. For more practical considerations, we further provide a detailed block diagram of a 2-D FIR filter using a recently proposed multiplier to reduce the roundoff quantization error in the logic-gate level. These proposed systolic structures amenable to VLSI implementation permit the 2-D input sequence to be scanned in row-wise mode and locally broadcast one value each clock per delay element.
SDGs
Type
journal article
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