Modeling power vertical high-k MOS device with interface charges via superposition methodology-breakdown voltage and specific ON-resistance
Journal
IEEE Transactions on Electron Devices
Journal Volume
65
Journal Issue
11
Pages
4947-4954
Date Issued
2018
Author(s)
Abstract
An analytical model for the power vertical MOS device with a high-k insulating dielectric (HKMOS) is derived via the superposition methodology on the condition of punchthrough. Considering three portions-the superjunction part, the p-i-n diode, and the interface charges at the heterointerface based on the conservation of electric displacement, the HKMOS device could be modeled well as verified by the 2-D simulation results. ? 2018 IEEE.
Subjects
Analytical models; Dielectric materials; Electric breakdown; Electric insulators; Electric potential; MOS devices; Permittivity; Semiconductor junctions; Electric displacement; Hetero interfaces; High dielectrics; Interface charge; Modeling power; PiN diode; Specific-on resistance; Superjunctions; High-k dielectric
Type
journal article