Design of a lower-error fixed-width multiplier for speech processing application
Resource
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Journal
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Pages
-
Date Issued
1999-06
Date
1999-06
Author(s)
Van, Lan-Da
Wang, Shuenn-Shyang
Tenqchen, Shing
Feng, Wu-Shiung
Jeng, Bor-Shenn
DOI
N/A
Abstract
A lower-error and lower-variance n/spl times/n multiplier is suitably proposed for VLSI design. Considering the next lower significant stage in P/sub n-1/ column and a useful error-compensation model in the least significant part, and utilizing a near optimized index to classify the error terms are our strategies in order to achieve lower error and variance as compared with previously proposed structure in the subproduct-array of the Baugh-Wooley algorithm. This novel structure applied to the fixed-width low-pass digital FIR filter for a speech signal processing system has excellent performance in reducing maximum error, average error, and variation of errors.
SDGs
Type
journal article
File(s)![Thumbnail Image]()
Loading...
Name
00778802.pdf
Size
291.34 KB
Format
Adobe PDF
Checksum
(MD5):4c11c9f5a4dbe48b934a3c86a77b6c64