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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
Novel 0.8V True-Single-Phase-Clocking (TSPC) Latches Using PD-SOI DTMOS Techniques for Low-Voltage CMOS VLSI Circuits
Details
Novel 0.8V True-Single-Phase-Clocking (TSPC) Latches Using PD-SOI DTMOS Techniques for Low-Voltage CMOS VLSI Circuits
Journal
IEEE SOI Conference Proceedings
Pages
63-64
Date Issued
2001-10
Author(s)
J. B. Kuo
T. Y. Chiang
JAMES-B KUO
DOI
10.1109/soic.2001.957986
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/294329
Type
conference paper