Novel 0.8V True-Single-Phase-Clocking (TSPC) Latches Using PD-SOI DTMOS Techniques for Low-Voltage CMOS VLSI Circuits
Journal
IEEE SOI Conference Proceedings
Pages
63-64
Date Issued
2001-10
Author(s)
Abstract
This paper reports two novel true-single-phase-clocking (TSPC) latches using partially-depleted (PD) SOI CMOS dynamic threshold (DTMOS) techniques for low-voltage CMOS VLSI circuits. Via controlling the body voltage dynamically the 0.8 V split-output PD-SOI TSPC latch using DTMOS techniques shows an 85% reduction in the switching time and less slow clock problems as verified by MEDICI simulation results.
SDGs
Type
conference paper