Design of a CMOS low-power and low-voltage four-quadrant analog multiplier
Journal
Analog Integrated Circuits and Signal Processing
Journal Volume
63
Journal Issue
2
Pages
307-312
Date Issued
2010
Author(s)
Liu, W.
Abstract
A New CMOS four-quadrant analog multiplier is presented in this paper. The proposed multiplier is suitable for low supply-voltage operation and its power consumption is also very low. The proposed circuit has been simulated with the HSPICE and simulation results are given to confirm the feasibility of the proposed analog multiplier. According to the simulation results, under the supply voltage of 1.5 V, the input range of the proposed multiplier can be 120 mV and the corresponding maximum linearity error is less than 3.2%. Moreover, the power dissipation of the proposed circuit is only 6.7 μW. The proposed circuit is expected to be useful in analog signal processing applications. © Springer Science+Business Media, LLC 2009.
SDGs
Type
journal article