A 12 Gb/s chip-to-chip AC coupled transceiver
Journal
Proceedings - IEEE International Symposium on Circuits and Systems
Pages
1692-1695
Date Issued
2011
Author(s)
Abstract
A differential AC coupled transceiver for high-speed and low-swing has been implemented in a 0.18μm CMOS process. The proposed architecture includes a pulse receiver and a broadband limiting amplifier to recover a NRZ signal from a 75fF capacitive coupled channel. The system works at 12Gb/s through 10cm FR4 printed circuit board interconnect, while dissipating only 13.5mW with a bit error rate less than 10 -12 .
SDGs
Type
conference paper