A 1.5 V CMOS high-speed 16-bit÷8-bit divider using the quotient-select architecture and true-single-phase bootstrapped dynamic circuit techniques suitable for low-voltage VLSI
Resource
Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on
Journal
Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on
Pages
-
Date Issued
1997-08
Date
1997-08
Author(s)
Yeh, C.C.
Lou, J.H.
Kuo, J.B.
DOI
N/A
Abstract
Based on a 0.8 /spl mu/m CMOS technology, the speed performance of this 16-bit/spl divide/8-bit divider circuit is improved by 45% as compared to the divider using the non-restoring iterative architecture and the domino dynamic logic circuits without the bootstrapped technique.
SDGs
Type
journal article
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