0.5V SOI DTMOS Technique for Design Optimization of Low-Power System Applications
Date Issued
2009
Date
2009
Author(s)
Lin, Chih-Hsiang
Abstract
This thesis reports DTMOS technique for design optimization of low-power system applications using nanometer bulk and SOI CMOS technologies. In Chapter 2, a 0.5V bulk PMOS dynamic-threshold technique enhanced with dual threshold (MTCMOS): BP-DTMOS-DT for design optimization of low-power system application using 90nm multi-threshold CMOS technology is presented. Via the BP-DTMOS type logic cell technique generated by the gate-level dual-threshold static power optimization methodology (GDSPOM) procedure, a 0.5V 16-bit multiplier circuit has been designed and optimized, showing a reduction of in 22% static power at the operating frequency of 250MHz as compared to the conventional HVT/LVT type counterpart optimized by the GDSPOM reported before. In Chapter 3, a 0.5V SOI CMOS dual-threshold circuit technique via DTMOS is explained for design optimization of low-power VLSI system applications. Via the DTMOS technology for implementing the SOI version of the GDSPOM, a 16-bit SOI multiplier circuit has been designed, showing a performance with 30% less power consumption as compared to the one designed purely in DTMOS, at VDD = 0.5V.
Subjects
SOC
low-power
DTMOS
BP-DTMOS
BP-DTMOS-DT
SOI
SOI DTMOS GDSPOM
0.5V
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-98-R96943094-1.pdf
Size
23.32 KB
Format
Adobe PDF
Checksum
(MD5):9042fccae3eee4eba06b6268f88cef9b