55MS/s 10位元 導管式類比數位轉換器之設計
Design of a 55MS/s 10-Bit Analog to Digital Converter with Pipeline Architecture
Date Issued
2005
Date
2005
Author(s)
Chang, Zeng-Wen
DOI
en-US
Abstract
Many of the applications nowadays utilize the digital signal processing to resolve the transmitted information like as wireless communication. Therefore, an analog-to-digital interface is required between the received terminal and the DSP system. With the explosive growth of wireless communication systems, Low power dissipation and high-speed transmission rate are becoming an increasingly important issue. Among many types of CMOS ADC architectures. A pipelined architecture can achieve good balance between power consumption and performance. This research focuses on low power dissipation and high speed ADC.
In this thesis, we design a 10-bit, and 55MSamples/s ADC. The ADC is implemented by a pipelined architecture with a resolution of 1.5-b/stage for digital error correction to obtain a 10-bit resolution at a sampling rate of 55MHz. The main sub-circuits of the ADC are sample-and-hold circuit, 2-bit flash A/D converter, 2-bit D/A converter, subtractor, multiply by two circuit, clock generator, encoder, register, and digital error correction. The sample-and-hold circuit is implemented with switched-capacitor techniques. The post-simulation results show that the overall circuit of ADC has 55MHz sampling rate, ±0.6LSB differential non-linearity, and ±0.7LSB integral non-linearity.
The pipelined ADC is fabricated with TSMC 0.35µm 2P4M n-well CMOS technology. The input range of the ADC is ±1V. The chip dissipates 62mW from a 3.3V supply. Total layout area is 1100um × 1400um.
Subjects
導管式類比數位轉換器
Pipeline ADC
Type
thesis
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