Formal-Assisted Buffer Insertion
Date Issued
2008
Date
2008
Author(s)
Wu, Kai-Chu
Abstract
Along with the progress of VLSI technology, buffer insertion plays an increasingly important role in improving circuit performance. Prior works (e.g. VGDP algorithm) are focused on enhancing the running time of buffer insertion algorithms, while our main objective in this thesis is to improve the solution quality. In contract to the traditional dynamic programming algorithms, we propose a formal-assisted buffer insertion (FABI) algorithm which can further improve circuit delay optimized by path-based VGDP buffer insertion. Experimental results show that block-based FABI has average 7.64 % circuit delay improvement over the path-based VGDP on ISCAS 85 benchmark circuits.
Subjects
buffer insertion
formal
Type
thesis
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ntu-97-R95921026-1.pdf
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