A Yield Improvement Methodology Using Pre- and Post-Silicon Statistical Clock Scheduling
Date Issued
2005-07-31
Date
2005-07-31
Author(s)
DOI
932215E002022
Abstract
In deep sub-micron technologies, process variations
can cause significant path delay and clock skew uncertainties
thereby lead to timing failure and yield loss. In this paper,
we propose a comprehensive clock scheduling methodology that
improves timing and yield through both pre-silicon clock scheduling
and post-silicon clock tuning. First, an optimal clock scheduling
algorithm has been developed to allocate the slack for each path
according to its timing uncertainty. To balance the skew that can
be caused by process variations, programmable delay elements
are inserted at the clock inputs of a small set of flip-flops on
the timing critical paths. A delay-fault testing scheme combined
with linear programming is used to identify and eliminate timing
violations in the manufactured chips. Experimental results show
that our methodology achieves substantial yield improvement over
a traditional clock scheduling algorithm in many of the ISCAS89
benchmark circuits, and obtain an average yield improvement of
13:6%.
Publisher
臺北市：國立臺灣大學電子工程學研究所
Type
report
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