Software-controlled cache architecture for energy efficiency
Resource
IEEE TRANSACTIONS ON CIRCUITS & SYSTEMS FOR VIDEO TECHNOLOGY 15 (5): 634-644 MAY 2005
Journal
IEEE Transactions on Circuits and Systems for Video Technology
Journal Volume
15
Journal Issue
5
Pages
634-644
Date Issued
2005
Author(s)
Abstract
Power consumption is an important design issue of current multimedia embedded systems. Data caches consume a significant portion of total processor power for multimedia applications because they are data intensive. In an integrated multimedia system, the cache architecture cannot be tuned specifically for an application. Therefore, a significant amount of cache energy is actually wasted. In this paper, we propose the software-controlled cache architecture that improves the energy efficiency of the shared cache in an integrated multimedia system on an application-specific base. Data types in an application are allocated to different cache regions. On each access, only the allocated cache regions need to be activated. We test the effectiveness of the software-controlled cache of the MPEG-2 software decoder. The results show up to 40% of cache energy reduction on an ARM-like cache architecture without sacrificing performance. © 2005 IEEE.
Subjects
Dynamic power dissipation; Energy consumption; MPEG-2; Multimedia applications; Software-controlled cache
SDGs
Other Subjects
Cache memory; Computer software; Decoding; Energy efficiency; Energy utilization; Image quality; Multimedia systems; Optimization; Cache energy; Dynamic power dissipation; MPEG-2 software decoder; Multimedia applications; Software-controlled cache; Embedded systems
Type
journal article