Design of 90nm Analog-to-Digital Converters for Low-Power and High-Speed Applications

Pipelined analog-to-digital converters (ADCs) and Successive-approximation register (SAR) analog-to-digital converters have been widely utilized in high speed communication system for mid to high resolution. This thesis proposes two circuit design techniques for analog-to-digital converters (ADCs), including pipelined ADC with hybrid calibration and successive-approximation register (SAR) ADC. According to the simulation and measurement results of the proof-of-concept prototypes, the proposed techniques are able to improve the operating speed. The proposed techniques and chip measurement results are sketched as follows:
The first technique is a pipelined ADC with hybrid calibration, a high speed and low power 10-bit pipelined ADC with 200MS/s sampling clock. This technique can reduce 50% of original calibration time and cost less hardware in high order calibration without changing communication system to accomplish high resolution, low power, and high speed ADC. Moreover, 1.5-bit architecture is applied to achieve high speed and low power application. Besides, the calibration not only increases the resolution, but also lowers the op-amps requirements of the gain and bandwidth.
A 10-bit, 200-MS/s pipelined ADC with the proposed calibration is implemented in a 90-nm 1P9M CMOS technology. According to the measuring results, with 1MHz input frequency, the ENOB and SFDR achieve 8.17 and 64.5dB at 10MS/s. The ENOB and SFDR are reduced to 7.46 and 46.7dB at 100MS/s with 1MHz input frequency. The ENOB and SFDR are reduced to 6.85 and 57.3dB at 100MS/s with 1MHz input frequency. The power consumption is 20.4mW at 200MS/s conversion rate.
The second design of SAR ADC utilizes the two-bit per step architecture technique operating at 100MS/s in 90nm to make this design a high speed, low power, and small area ADC(without using excessive power.). As we know, the comparator only outputs high and low voltage, so we prepare these two voltages to choose beforehand. Therefore, we are able to decide two bit in one cycle but not one bit in conventional. Compared to converters that use the conventional architecture, the operating speed is increase by about 70%. But compared to time-interleaved SAR ADC, the total sampling capacitor could be reduced by 25%.
A 9-bit, 100-MS/s SAR ADC with the proposed two-bit per step switching procedure is implemented in a 90-nm 1P9M CMOS technology. According to the measuring results with 20MHz input frequency, the ENOB and SFDR achieve 6.77 and 44.71dB at 50MS/s. The ENOB and SFDR are reduced to 6.05 and 45.86dB at 100MS/s with 10MHz input frequency. The power consumption is 2.4mW at 100MS/s conversion rate.