Design of High-Speed CMOS Clock Generation and Data Recovery Circuits
Date Issued
2007
Date
2007
Author(s)
Liang, Che-Fu
DOI
en-US
Abstract
ABSTRACT
With the progress of the CMOS technologies and the increasing demand for high-speed data communications, new specifications utilizing wider bandwidth than before spawns and the needs for high-performance analog circuits augment as well. The long-standing phase-locked loop (PLL) and its high-speed applications play major roles in these designs. Though relating techniques for PLL have prospered for years, new system architectures and circuit topologies are still desired to overcome the ever-increasing speed limitation.
Hence, in this dissertation we focus on the design and application of phase-locked systems for high-speed wireless or wire-line applications, including clock generation and data recovery circuits. Several system architectures and circuit topologies are proposed to alleviate the design bottleneck on high-speed CMOS transceivers.
First, a digital technique with auto-tracking ability is presented to calibrate the current mismatch of the charge pump in phase-locked systems. A 5GHz frequency synthesizer is used to justify the proposed calibration technique. It has been has been implemented in 0.18µm CMOS. The measured output spur is suppressed by 5.35dB at 5.2GHz after the calibration circuits are active. The measured output spur levels are less than -68.5 dBc throughout the whole output frequency range. The measured phase noise is -110dBc/Hz at an offset frequency of 1MHz.
Next, a 14-band frequency synthesizer for ultra-wideband (UWB) applications has been implemented in 0.18µm CMOS. The unwanted spurs due to frequency mixing are at least –35dB lower than the output carriers by using a quadrature divide-by-3 circuit and a two-stage single-sideband mixer. The core circuit area is 1.5 mm2 and total power consumption is 160mW.
Hereafter, a 10Gbps inductorless burst-mode clock and data recovery (BMCDR) circuit using a gated digital-controlled oscillator has been fabricated in 0.18µm CMOS. The digitally frequency-calibrated architecture is adopted to save the power consumption and chip area. The CDR circuit occupies an active area of 0.16mm2 and draws 36mW from a 1.8V supply. The measured rms jitter and peak-to-peak jitter is 8.5ps and 42.7ps, respectively.
With the knowledge of BMCDR circuits, a jitter-tolerance-enhanced 10Gb/s clock and data recovery (CDR) circuit is presented. By using a gated-digital-controlled oscillator (GDCO), the proposed GDCO-based phase detector achieves a wide linear range and its jitter tolerance is enhanced by a factor of 2 without sacrificing the jitter transfer. The prototype chip has been fabricated in 0.13µm CMOS and consumes 60mW from a 1.5V supply. It occupies an active area of 0.36mm2. Measurements on the testchip demonstrate an rms jitter of 0.96ps and a peak-to-peak jitter of 7.11ps with a 27-1 PRBS. Finally, we conclude this dissertation.
Subjects
鎖相迴路
頻率合成器
時脈與資料回復電路
Phase-Locked-Loop
Frequency Synthesizer
Clock and Data Recovery Circuit
Type
thesis
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