An Inductor-less 20 Gb/s AC Coupled Chip-to-Chip Interconnect

Today, the scaling of MOS transistor dimensions is a key factor in the improvement of performance of CMOS technology. High speed links with small AC coupling capacitances are increasing in importance. As a result, the receiver receives a stream of positive and negative pulses corresponding to the rising and falling edges of transmitted data. Receivers which are capable of recovering NRZ signals from these narrow pulses are referred to in this work as AC coupled receivers, and are not to be confused with receivers for links with a relatively large DC blocking capacitor where the received waveforms still look like an NRZ signal with some baseline wander.
This thesis introduces a high-speed 12 Gb/s AC coupled receiver architecture for high density interconnects and a modified design for the 1st design which can operate at the 20Gb/s. The proposed architecture combines a novel hysteresis circuit path and a linear broadband amplifier path to recover a NRZ signal from a 75fF capacitor coupled channel. Due to the small coupling capacitances, the transmitted NRZ data at high frequency transitions can be detected at the receiver. The main challenge of the receiver front end is to recover NRZ data from the low swing pulses.
In conclusion, 2 chips are designed and fabricated in TSMC 90nm CMOS technology. The 1st proposed chip is using a novel hysteresis circuit path without any compensation technique. The 2nd proposed chip improve the 1st chip integrated with time domain compensation.
In addition, we also designed a Low dropout, low quiescent current, output capacitor-less regulator showed in appendix.