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College of Electrical Engineering and Computer Science / 電機資訊學院
Electronics Engineering / 電子工程學研究所
Delay modeling for buffered RLY/RLC trees
Details
Delay modeling for buffered RLY/RLC trees
Journal
2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test
Journal Volume
2005
Pages
237-240
Date Issued
2005
Author(s)
Wang, S.-L.
YAO-WEN CHANG
DOI
10.1109/VDAT.2005.1500064
URI
http://www.scopus.com/inward/record.url?eid=2-s2.0-33745470870&partnerID=MN8TOARS
http://scholars.lib.ntu.edu.tw/handle/123456789/316489
Type
conference paper