Delay modeling for buffered RLY/RLC trees
Journal
2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test
Journal Volume
2005
Pages
237-240
Date Issued
2005
Author(s)
Wang, S.-L.
Abstract
For deep-submicron, high-performance circuits, the inductive effect plays a very important role in determining the circuit delay. In this paper, the authors derived accurate formulae for modeling the delays of buffered RLY/RLC wires and trees. The formulae could handle balanced and unbalanced trees and consider buffer insertion. Extensive simulations with HSPICE show that the formulae have high fidelity, with an average error of within 5.51% based on the 180 nm technology. The simulations show that the formulae are more accurate than previous works.
Type
conference paper