Design of a Timing Recovery and Performance Analysis for 10GBASE-T Ethernet System

This thesis proposes a symbol timing recovery architecture using non-loop timing scheme for 10GBASE-T Ethernet System (IEEE 802.3an). The timing error detector and the interpolator architecture are discussed in this thesis. In order to achieve the four-pair synchronization in the 10GBASE-T Ethernet System, two symbol timing recovery architectures are presented, including conventional (a single digital phase-locked loop accompanies with multiple delay-locked loops) one and average sampling phase one. In addition, a symbol timing recovery with reduced loop delay is proposed. It is able to lower the jitter of the recovered symbol clock and recover larger sampling frequency offset at the analog-to-digital converter. The performance of these symbol timing recovery architectures is compared in terms of the decision point signal-to-noise ratio (dpSNR) of an existing software 10GBASE-T receiver architecture. Simulation results show that the proposed architectures can meet the requirement of minimum dpSNR and achieve the bit-error-rate specification in the standard.