Design and Performance Analysis of an Asynchronous Combined-Input-Output-Queued Packet-Based Switch for Variable-Length Packet Unicast and Multicast Switching

Currently most of the switches are cell-based and synchronous,such that the length of the packet is fixed. However, a great partof the current network traffic consists of variable lengthpackets, for example, Ethernet or IP traffics. Hence, thecell-based switch must segment the incoming packets at the inputports into cells, switch these cells synchronously, reassemblethem at the output ports, and finally transmit the packets to theoutput links. The additional segmentation and reassembly circuitsare required. The synchronous cell-based switch incurs performancedeterioration due to synchronization and segmentation overheadwhen the input traffic consists of variable length packets. Inorder to switch the incoming packets with variable lengthasynchronously, we propose a novel switch architecture in thisthesis. Its performance is analyzed in detail by queueing theoryand simulation. The system parameters are optimized to attain thebest performance with the minimum cost.

In general, we can categorize the switch architecture as InputQueued (IQ), Output Queued (OQ), or Combined Input Output Queued(CIOQ) switch according to the position of the buffers. The IQswitch is simplest but its throughput is rather low because of theHead-Of-the-Line (HOL) blocking effect. The HOL blocking can beeliminated completely in an OQ switch, which stores the packets inthe output ports. However, the operation speed of the OQ switchmust be many times the rate of the input link in order to obtainhigh throughput. The required speedup of the switch operationrequires extreme short access time of the buffer memory. The speedof the transmission link increases fast because of thecontinuously growing network bandwidth demand and the advent ofWavelength Division Multiplexing (WDM) technology. However, thebottleneck of the network performance still exists because of thelack of high speed switches with large ports. The requirement ofextreme high switching operation speed makes an OQ switchinfeasible. Hence, a lot of schemes were proposed in theliterature to improve the performance of CIOQ switches, whichdon't require the speedup of switching speed too much. However,these schemes require complicated control unit and thus aredifficult to implement. The key to success for a high capacity andhigh performance switch is a simple hardware design to arbitratethe contending packets and to control the routes of packets withthe switching fabric. The design goal of the proposed switch inthis thesis is to switch variable length packets asynchronouslywith simple and feasible hardware. We also take into account thescalability of the switch, i.e., the switch design is based on amodular architecture. There is neither packet arrivalsynchronization circuits nor central controllers, which arerequired in the conventional cell-based switches. Modularswitching elements and simple input controllers are used to switchpackets asynchronously.

The proposed switch provides unicast and multicast capabilitiesfor variable length packets. We theoretically analyze and obtainthe performance metric in closed form. Computer simulations aredone to verify the theoretical results. We also derive the optimalsystem parameters, which can be used as the design rule of theswitch. Moreover, we present a circuit level design of the switcharchitecture, which integrates the unicast and multicastcapabilities. This complete design also takes into account Qualityof Service(QoS) provision and packet sequence integrity afterswitching. We believe that the proposed switch is easy toimplement and can satisfy the requirement of high capacity in themodern high speed network.