IC HTOL Test Stress Condition Optimization
Resource
Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on
Journal
19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’04)
Pages
272-279
Date Issued
2004-10
Author(s)
Abstract
HTOL (high temperature operation life) test is used to determine the effects of bias and temperature stress conditions on solid-state devices over time. It simulates the devices' operating condition in an accelerated manner, and is primarily for device reliability evaluation. This paper addresses an SA (simulated annealing) method used for the HTOL test stress condition decision-making that is an optimization problem. The goal is to reduce the resources for the HTOL test, hardware or time, under reliability constraints. The theory of the reliability statistical model and the SA algorithm are presented. In our optimization algorithm, we need to calculate the accurate HTOL stressed power for the next optimization loop since the Vs (stressed voltage) that is optimized will affect not only Afv (voltage acceleration factor) but also Aft (thermal acceleration factor). A curve-fitting algorithm is applied to get reasonable accelerated factors and reliability calculations. The model selection process and statistical analysis of fitted data by different models are also presented. Experimental results with different stress condition priorities and different user settings are given to demonstrate the effectiveness of our approach.
Type
conference paper
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