A digital bang-bang phase-locked loop with bandwidth calibration
Journal
2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings
Date Issued
2016
Author(s)
Abstract
A digital bang-bang phase-locked loop (BBPLL) with bandwidth calibration is presented. The proposed bandwidth calibration circuit adjusts the proportional and integral gain of the digital loop filter to tolerate the process, voltage and temperature (PVT) variations. This BBPLL is fabricated in 40-nm CMOS technology. Its active area is 0.0049 mm 2 and the power is 3.34 mW from a supply of 1.1 V. The reference frequency is 250 MHz and the output frequency is 5 GHz. The integrated RMS jitter is 1.242 ps.
SDGs
Type
conference paper