Memory efficient architecture for belief propagation based disparity estimation
Journal
IEEE International Symposium on Circuits and Systems
Journal Volume
2015-July
Pages
2521-2524
Date Issued
2015
Author(s)
Abstract
This paper introduces a memory efficient architecture for belief propagation based disparity estimation. To find the bottleneck of the memory, a lifetime analysis of the exchanged message is presented. The analysis leads to architecture which can take advantage of the data characteristics resulting in memory reduction, computing resource and memory access. In the experimental result, the proposed architecture gains 20% speed up in software simulation compared to non-optimized counterpart. In hardware implementation, more than 42% area is reduced by this architecture design without affecting the performance. With further design effort 61.8% area reduction is achieved.
Type
conference paper